As integrated circuit complexity increases, the dimensions of the devices within the circuit necessarily decrease. Although one generally first thinks of reducing the source, gate and drain dimensions of field effect transistors, another device element whose dimension must also be shrunk is the thickness of the gate dielectric. Thicknesses less than several tens of nanometer are desirable for many of these device elements. However, as the gate dielectric becomes thinner, the importance of dielectric quality, including both low defect density and dielectric processing sensitivity, becomes greater with respect to device performance. Low defect density and processing sensitivity are, of course, also important in other integrated circuit applications.
In fact, in VLSI circuits, the quality of dielectric layers ultimately becomes a dominant factor in determining device performance. A field effect transistors (FETs) uses a voltage applied to a gate electrode, which is electrically insulated from the channel region by the thin gate dielectric layer situated beneath the gate electrode, to control current flow in a channel between source and drain regions. If the source and drain regions have n-type conductivity, a positive gate voltage, V.sub.g, induces negative charges in the channel, and current flows in the channel when the gate voltage exceeds the threshold voltage. In an ideal FET, the gate voltage may be arbitrarily large with no current flow through, and charge storage, in the dielectric. In practice, however, it is impractical to eliminate trapped charges in the dielectric, which cause operating instabilities due to charge induced shifts in the threshold voltage. This shift may be better understood from the following considerations. The voltage shift due to the trapped charges is proportional to Q.sub.t /C, where Q.sub.t is the trapped charge and C is the capacitance. Although the voltage shift decreases as the oxide thickness decreases, the compensation for trapped charges need not be reduced in the scaling to smaller dimensions. In fact, charge trapping, and defect induced dielectric breakdown set the scaling limits for thin oxides. It is thus essential that the number of defects in the dielectric be minimized for best device performance. However, at least one semiconductor device manufacturer has reported that the defect density, in particular, pinholes, increases with decreasing silicon oxide thickness once the oxide was less than 20 nm thick. Presently, silicon oxide, SiO.sub.2, is the most commonly used dielectric material, at least for Si integrated circuits, and may be formed either by thermal growth or material deposition. Thermal oxidation of silicon involves a reaction of the oxide/silicon interface that is driven by inward movement of the oxidizing species. Thus, the silicon surface is continually renewed and the bulk SiO.sub.2 is maintained with sufficient oxygen to remove the majority of the bulk and surface defects. Surface passivation reduces the number of states within the bandgap by lowering the number of dangling bonds because a stable SiO.sub.2 film is formed.
Although deposited films can be formed more quickly than thermal oxides, the dielectric qualities of deposited films are generally inferior to those of thermally grown oxide films. Thus, deposited oxides have not been used as dielectrics because they typically have a higher defect density, lower breakdown fields, and high interface state densities. However, a low temperature plasma enhanced chemical vapor deposition process was reported as yielding a moderately high quality SiO.sub.2 layer. See JOURNAL OF APPLIED PHYSICS 3136-3145 (Nov. 1, 1986). The interface trap density was reduced by a fast deposition anneal. Other deposition processes generally have an annealing step to both densify the oxide and improve its electrical integrity, but the results have not been as good as is desired if the oxide will be used as a gate dielectric. Another method of forming a gate dielectric involves growing an oxide film on the silicon substrate, depositing a thin oxide film on the grown oxide and then performing an anneal step in an oxygen ambient to form a thermally grown oxide layer between the grown oxide layer and the silicon substrate. See U.S. Pat. No. 5,153,701. A problem with this method is that deposited oxides are, typically, more prone to electron trapping than grown oxide films.